Switching mode power converters of the prior art, as illustrated in FIG. 1, produce large harmonic current, generating interference in communication circuits and may also produce excessive neutral current, hot spots in the transformer, resonance, inaccuracies in the instrumentation, mis-operation of relays and voltage distortion in the power distribution system. With the increase of such nonlinear loads connected to the power grid, efficient techniques for power factor correction (PFC) are increasingly sought after to deliver more power to the load at a constant level.
For switching mode power converters the output voltage is controlled by an electronic circuit which measures a level of electric current within the circuit, compares that measured level to a predetermined desired level, and develops a response to that measurement elsewhere in the circuit in order to more accurately achieve the desired level. A boost converter power stage of the prior art is illustrated in FIG. 1. The input voltage VIN is coupled to the input terminals 10 and 12. The input terminal 10 is coupled to a first terminal of the inductor L1. A second terminal of the inductor L1 is coupled to the positive terminals of the switches SW1 and SW2. The switch control voltage SCV1 is coupled to control the switch SW1 and to the input of the inverter 18. The output of the inverter 18 is coupled as the switch control voltage SCV2 for controlling the switch SW2. The capacitor C1 is coupled between the negative terminals of the switches SW1 and SW2. The load RL is coupled across the capacitor C1 and the output voltage VOUT can be measured across the output terminals 14 and 16. This power stage is designed so that when the switch SW1 is closed, the switch SW2 is open and when the switch SW1 is open, the switch SW2 is closed.
The boost converter of FIG. 1 converts the input voltage VIN to a desired output voltage VOUT. The voltage VIN is applied to a pair of terminals 10 and 12 of the boost power stage. The input voltage VIN is turned on and turned off relative to the boost power stage by alternately closing and opening the switches SW1 and SW2. The switches SW1 and SW2 are controlled by the switch control voltage signals SCV1 and SCV2. The circuit is designed so that when the switch SW1 is open, the switch SW2 is closed and when the switch SW1 is closed, the switch SW2 is open. The input voltage VIN is isolated from the load RL by the inductor L1 so that the switching noise is not readily coupled to the input line.
The output voltage VOUT is established by integrating the inductor current in the LC filter network. This integrated current is supplied to the load circuit as the converted output voltage VOUT. In order to establish the proper output voltage from a given input voltage, the input voltage VIN is switched in and out of the circuit by the switches SW1 and SW2. The resulting oscillating signal is integrated in the LC network to form the desired output voltage VOUT. If the input voltage VIN changes or varies over time, the frequency at which the switches SW1 and SW2 are opened and closed can also be varied in order to maintain the desired output voltage VOUT.
When the switch SW1 is open and the switch SW2 is closed the input voltage VIN is connected to the remainder of the circuitry and the inductor current IL rises linearly until it reaches the peak current level. When the inductor current IL reaches the peak current level, the switch SW1 is closed, the switch SW2 is open and the inductor current IL decreases at a linear rate. The linear rise and fall rates for the inductor current IL need not be the same. Once the current has fallen to the minimum level, the circuit is "turned on", by opening the switch SW1 and closing the switch SW2, and the cycle is then repeated. The output voltage VOUT is equal to the average of the inductor current IL multiplied by the load resistance RL. The inductor current IL is integrated by the LC network forming the output voltage VOUT.
The boost converter, as illustrated in FIG. 1, is typically used in power factor correction circuits of the prior art because the input current flows through an inductor and is therefore relatively smooth and easy to control. However, since the input instantaneous power does not equal the output instantaneous power, the intermediate stage consisting of the capacitor C1 must be installed to store the excess instantaneous power temporarily. Because the system typically must interface with a universal input such as an offline AC source, the capacitor C1 must have the ability to sustain a very high output voltage of approximately 380 VDC. Such capacitors are typically very expensive. Isolation of the boost converter is difficult to implement because such a high PFC output voltage is required. In order to implement isolation of the boost converter, a second stage comprising a step down power converter with isolation is required.
The cascade connection of power stages is a very effective and powerful tool in the design of state-of-the-art high frequency switching mode power converters. Power factor corrected power supplies offer improved performance when compared to ordinary off-line switching power supplies. However, the system stability of such power factor corrected power supplies needs special care.
Systems which contain a right hand zero are referred to as non-minimum phase systems. It is difficult to compensate for a cascade power stages system, because of the right hand zero and the two close poles which are caused by a momentary no load. For example in the single boost power converter stage illustrated in FIG. 1, the load of this stage RL is continuously connected to the output stage. Because the load RL is also part of the output filter, it is very important to the switching power converter. Reduction of the load will cause the poles due to the inductor and the capacitor to become closer and thus reduce the phase margin.
A cascade connection of two power stages is illustrated in FIG. 2. The input voltage VIN is coupled to the terminals 20 and 22. The terminal 20 is coupled to a first terminal of the inductor L1. The second terminal of the inductor L1 is coupled to the positive terminals of the switches SW1 and SW2. The switch control voltage SCV1 is coupled to control the switch SW1 and to the input of the inverter 28. The output of the inverter 28 is coupled as the switch control voltage SCV2 for controlling the switch SW2. The capacitor C1 is coupled between the negative terminals of the switches SW1 and SW2. The positive terminal of the switch SW3 is coupled to the capacitor C1 and the negative terminal of the switch SW2. The negative terminal of the switch SW3 is coupled to the positive terminal of the switch SW4 and to a first terminal of the inductor L2. The capacitor C2 is coupled between a second terminal of the inductor L2 and the negative terminal of the switch SW4. The switch control voltage SCV3 is coupled to control the switch SW3 and to the input of the inverter 30. The output of the inverter 30 is coupled as the switch control voltage SCV4 for controlling the switch SW4. The load RL is coupled across the capacitor C2 and the output voltage VOUT can be measured across the terminals 24 and 26.
In the cascade power stage, as illustrated in FIG. 2, the load RL could be momentary and not constant, causing periods when there is no load. Without the load connected to the power stage, the system will oscillate and cannot maintain a constant output voltage VOUT. Many systems of the prior art attempt to reduce the no load period by speeding up the loop response for the second stage. A second, faster clock, is typically used to speed up the response of the second stage, causing the system to become more complicated.
A trailing edge modulation control scheme is illustrated in FIG. 3. The converter stage of this trailing edge scheme is the same as the converter stage of FIG. 1 with the addition of the switch control circuitry 31. A reference voltage REF is coupled to the positive input of the error amplifier U3. The negative or inverting input of the error amplifier U3 is coupled to the potentiometer PT1. The output VEAO of the error amplifier is coupled as the positive input of the comparator U1. The negative input of the comparator U1 is coupled to the ramp output of the oscillator U4. The output of the comparator U1 is coupled as the reset input R of the flip flop U2. The input D of the flip flop U2 is coupled to the output Q. The clock input CLK of the flip flop U2 is coupled to the clock output of the oscillator U4. The output Q of the flip flop U2 is coupled to control the operation of the switch SW1.
Pulse width modulation (PWM) is a technique used to maintain a constant output voltage VOUT when the input voltage does not remain constant and varies over time. By changing the frequency at which the switches are opened and closed, as the input voltage changes, the output voltage VOUT can be maintained at a constant level as desired. The inductor current IL is stored as a voltage level on the plates of the capacitor C1. Because of its parallel connection to the output of the circuit, the voltage across the capacitor C1 is equivalent to the output voltage VOUT and the voltage across the potentiometer PT1. A fraction of that voltage is measured from the potentiometer PT1 forming the voltage VEA which is input into the negative terminal of the error amplifier and is compared to the reference voltage REF. This comparison determines how close the actual output voltage VOUT is to the desired output voltage.
Conventional pulse width modulation techniques use the trailing edge of the clock signal, so that the switch will turn on right after the trailing edge of the system clock. FIGS. 4, 5 and 6 show corresponding voltage waveforms with respect to time of different voltage levels at different points within the switch control circuitry 31. The time axis for the FIGS. 4, 5 and 6 has been drawn to correspond in all three figures. FIG. 4 illustrates the voltage levels with respect to time of the error amplifier output VEAO and the modulating ramp output of the oscillator U4. FIG. 5 illustrates the voltage level of the switch SW1 with respect to time. The switch SW1 is at a high voltage level when it is "on" or closed. The switch SW1 is at a low voltage level when it is "off" or open. FIG. 6 illustrates the clock impulses with respect to time of the clock output of the oscillator U4.
The switch SW1 will turn on after the trailing edge of the system clock. Once the switch SW1 is on, the modulator then compares the error amplifier output voltage and the modulating ramp; when the modulating ramp reaches the error amplifier output voltage, the switch will be turned off. When the switch is on, the inductor current will ramp up. The effective duty cycle of the trailing edge modulation is determined during the on time of the switch. FIG. 3 illustrates a typical trailing edge control scheme using a single boost power converter stage. As the input voltage VIN varies over time, the duty cycle or time that the switch SW1 is on will vary in order to maintain a constant output voltage VOUT.
A leading edge modulation control scheme is illustrated in FIG. 7. The difference between the circuit of FIG. 3 and the circuit of FIG. 7 is that the reference voltage in the circuit of FIG. 7 is coupled to the negative input of the error amplifier U3 and the voltage VEA from the potentiometer PT1 is coupled to the positive input of the error amplifier U3. FIGS. 8, 9 and 10 show corresponding voltage waveforms with respect to time. FIG. 8 illustrates the voltage levels with respect to time of the error amplifier output VEAO and the ramp output of the oscillator U4 for the leading edge modulation circuit of FIG. 7. FIG. 9 illustrates the voltage level of the switch SW1 with respect to time. The switch SW1 is at a high voltage level when it is "on" or closed. The switch SW1 is at a low voltage level when it is "off" or open. FIG. 10 illustrates the clock impulses with respect to time.
In the case of leading edge modulation, the switch SW1 is turned off after the leading edge of the system clock; when the modulating ramp reaches the level of the error amplifier output voltage VEAO, the switch will be turned on. The effective duty cycle of the leading edge modulation is determined during the off time of the switch. FIG. 7 shows a typical leading edge control scheme using a single boost power converter stage. While the voltage waveforms for the switch SW1 shown in FIGS. 5 and 9 show a constant duty cycle for the switch SW1, as the input voltage VIN varies over time, the time that the switch SW1 is on or closed, will vary in order to maintain a constant output voltage VOUT level.
Ripple voltage is a quantity used to measure the amount of AC voltage introduced into the DC output voltage. If the boost-buck cascade power converter as illustrated in FIG. 2 is used as the offline PFC-PWM power converter, the ripple voltage of the PFC output stage can be separated into two portions. The first portion is due to the voltage drop across the ESR which corresponds to the capacitor C1 and C2. The second portion of the ripple voltage is due to the change in voltage with respect to time across the capacitor C1. Prior art schemes control the switches SW1 and SW3 with two separate clock signals, so that the switch SW1 and the switch SW3 are opened and closed at different times. If both converters are in the continuous conduction mode (CCM) and the conventional trailing edge modulation scheme with two different clocks controlling the switches SW1 and SW3 is used, the ripple voltage is ##EQU1## Where, the maximum current I.sub.2max through a closed switch SW2 is equal to ##EQU2## When the input phase is equal to 60 degrees, the change in voltage dV across the capacitor C1 reaches a maximum if the second portion of the ripple voltage which corresponds to the change in voltage across the capacitor C1 is dominant.
Each of the switches used has an associated parasitic capacitance which causes a loss of the power transferred to the output circuit. The parasitic capacitance of the switch builds up a stored voltage when the switch is open. This voltage is then discharged when the switch is closed, causing a loss of the power that was stored in the parasitic capacitance of the switch.
What is needed is a synchronous switching method for a cascade connected power converter which utilizes a single clock reference signal and reduces the ripple voltage in order to facilitate more efficient power usage and lower harmonic content in the line current. What is further needed is a method for capturing a portion of the voltage lost due to the parasitic capacitances of the switches.